This invention relates to a semiconductor device such as SRAM (Static Random Access Memory), and a method of manufacturing the same.
Conventionally, a soft error (hereinafter, may be abbreviated as SER) caused by an xcex1-ray often takes place with high-integration of a SRAM device in a semiconductor device of the type as described.
More specifically, when a memory cell is reduced in size in order to highly integrate the SRAM device, a current per a unit memory cell is reduced. On the other hand, the xcex1-ray emitted from natural uranium or the like is irradiated into a semiconductor memory device.
Herein, it is noted that the natural uranium is slightly contained in a ceramic package or a cover for sealing the semiconductor memory device.
Thereby, a large number of electron-hole pairs are generated in a substrate. Consequently, the electron being generated moves in the substrate and destroys information (namely, electric charge) stored in the memory cell. This results to an error operation of the semiconductor memory cell.
Referring to FIG. 1, description will be made about a basic structure of a high-resistance load type memory cell serving as a main part of the related SRAM device.
The SRAM device includes a pair of transfer transistors ST1 and ST2, a pair of driving transistors DT1 and DT2, and a pair of load resistors L1 and L2.
In the transfer transistor ST1, one terminal (source or drain) is connected to a bit line BL1 while the other terminal (source or drain) is connected to a node N1. Further, the gate electrode terminal is connected to a word line WL1.
In the transfer transistor ST2, one terminal (source or drain) is connected to a bit line BL2 while the other terminal (source or drain) is connected to a node N2. Further, the gate electrode terminal is connected to a word line WL2.
In the driving transistor DT1, one terminal (source or drain) is connected to a reference voltage Vss while the other terminal (source or drain) is connected to the node N1. Further, the gate electrode terminal is connected to the node N2.
In the driving transistor DT2, one terminal (source or drain) is connected to a reference voltage Vss while the other terminal (source or drain) is connected to the node N2. Further, the gate electrode terminal is connected to the node N1.
In the load resistor L1, one terminal is connected to a power supply voltage Vcc while the other terminal is connected to the node N1.
In the load resistor L2, one terminal is connected to the power supply voltage Vcc while the other terminal is connected to the node N2.
Further, a capacitor C1 is coupled to the node N1 while a capacitor C2 is coupled to the node N2.
For example, a NMOS may be used as each of the transfer transistors ST1, ST2, and the driving transistors DT1, DT2.
Subsequently description will be made about a SER resistance in such high-resistance load type memory cell.
In the case of the resistance load type memory cell, the SER resistance is generally determined in dependence upon a current IL flowing through the load resistor L1, L2 and node capacitance C1, C2.
When the node N1 is put into a high state and a voltage is equal to V1h in the memory cell, the current IL flowing through the load resistor L1 and the node capacitance C1 has the following relationship with the SER resistance.
Namely, in the case where the bit line BL1 is put into the power supply voltage Vcc, when the transfer transistor ST1 is turned on, the voltage V1h of the node N1 is reduced with about a threshold voltage Vt of the transfer transistor ST1 from the power supply voltage Vcc to become Vccxe2x88x92Vt.
Under this circumstance, if the current sufficiently flows through the load resistor L1 from the power supply voltage Vcc, the voltage V1h is more increased to the power supply voltage Vcc.
In such a memory cell, when the transfer transistor ST1 is turned on and the voltage V1h is reduced from the power supply voltage Vcc to Vccxe2x88x92Vt, the probability of the occurrence of the decrease in the voltage V1h, in which the voltage is reduced from the power supply voltage Vcc to the Vcxe2x88x92Vt, may be lowered as the node capacitance C1 becomes higher.
In addition, such a time that the voltage V1h further restores to the power supply voltage Vcc by the power supply voltage Vcc of the power supply becomes rapider, as the current IL flowing through the load resistor L1 is higher and as the node capacitance C1 is higher.
Hereinafter, description will be made about a method of manufacturing the high resistance load memory cell with reference to FIGS. 2 through 7.
Herein, only a region around the node N1 of the memory cell in FIG. 1 is illustrated in FIGS. 2 through 7, and the illustration of the peripheral circuit portion is omitted.
Referring to FIG. 2, a thick device isolation silicon oxide film 2 is formed to a thickness of 400 nm by the use of Local Oxidation of Silicon (LOCOS) method on a principal surface of a silicon substrate 1.
Thereafter, only region for forming a memory cell region, a transfer transistor, and a driving transistor (namely, NMOS) are opened by the use of the photolithography technique.
Subsequently, impurity (boron) is implanted so as to form a P-type well region 21 by the ion-implanting technique.
In this event, the ions are implanted within a concentration range between 1xc3x971013 and 2xc3x971013 [cmxe2x88x922] and within an accelerating voltage range between 250 and 350 [Kev].
Although not illustrated, the ions are implanted to form the device isolation region at the same time, and a P-type impurity region is formed under the device isolation silicon oxide film 2. Further, the ions are also implanted so as to control the voltage Vt.
Thereafter, the silicon substrate 1 is thermally oxidized to form a gate silicon oxide film 3 to a thickness of about 8 nm. Successively, a polysilicon film is deposited to a thickness of about 100 nm of the gate silicon oxide film 3 by the use of CVD technique.
Subsequently, compound (namely, silicide) between Ti or W serving vas a high-melting point metal and silicon is deposited to a thickness of about 100 nm by thermally diffusing phosphorus to form a polyside.
Further, the gate electrode 4 is patterned by the use of the photolithography technique.
Referring to FIG. 3, only a region for forming the memory cell region, the transfer transistor and the driving transistor (namely, NMOS) is opened by the use of the photolithography technique.
Thereafter, impurity (phosphorus) is implanted in a self-alignment. manner using the gate electrode 4 as a mask by the ion implanting technique to form an N-type low concentration impurity region 5.
In this case, the ions are implanted within the concentration range between 1xc3x971013 and 3xc3x971013 [cmxe2x88x922] and within the accelerating voltage range between 15 and 25 [Kev].
Next, the silicon oxide film 6 is formed within the thickness range between 100 and 150 nm on the device isolation silicon oxide film 2, the gate silicon oxide film 3, and the gate electrode 4 by the use of the CVD technique.
Successively, referring to FIG. 4, the silicon oxide film 6 is etched-back by the use of the etching technique to form a sidewall silicon oxide film 7 at the sidewall of the gate electrode 4.
Thereafter, only a region for forming the memory cell region, the transfer transistor and the driving transistor (namely, NMOS) is opened by the use of the photolithography technique.
Subsequently, impurity (phosphorus) is implanted in a self-alignment manner using the gate electrode 4 and the sidewall silicon oxide film 7 as a mask by the ion implanting technique to form a N-type high concentration impurity region 8.
In this case, the ions are implanted within the concentration range between 1xc3x971015 and 5xc3x971015 [cmxe2x88x922] and within the accelerating voltage range between 30 and 40 [Kev].
Next, the silicon oxide film 9 is formed within the thickness range between 100 and 150 nm on the device isolation silicon oxide film 2, the gate silicon oxide film 3, and the gate electrode 4 by the use of the CVD technique.
Further, a TEOS.BPSG film 10 having excellent reflow characteristic is deposited to a thickness of about 500 nm on the silicon oxide film 9 by the use of the CVD technique.
Thereafter, a reflow is performed for about 30 to 60 minutes within the temperature range between 800 and 900xc2x0 C., and the surface of the TEOS.BPSG film 10 is flattened. In this event, the flattening process is carried out such that a wiring layer of a polysilicon film 14 (will be formed later) is not short-circuited.
Subsequently, referring to FIG. 5, a contact hole 11 is opened for the silicon oxide film 9 and the TEOS.BPSG film 10 by the etching technique. Thereinafter, impurity (phosphorus) is partially implanted into the N-type high concentration impurity region 8 under the contact hole 11 by the use of the ion implanting technique to form the N-type high impurity region 12.
In this case, the ions are implanted within the concentration range between 1xc3x971014 and 1xc3x971015 [cmxe2x88x922] and within the accelerating voltage range between 40 and 60 [Kev].
Through the contact hole 11, the diffusion layers of the driving transistor DT1 and the transfer transistor ST1, the load resistor L1, and the gate electrode of the driving transistor DT2 illustrated in FIG. 1 are connected to each other.
Herein, the ions are implanted so as to reduce contact resistance between the load resistor L1, the diffusion layers of the driving transistor DT1 and the transfer transistor ST1 and the gate electrode of the driving transistor DT2.
Further, referring to FIG. 6, the polysilicon film 14 is deposited to a thickness within the range between 100 and 150 nm on the N-type high concentration impurity region 12 and the TEOS.BPSG film 10 by the CVD technique.
Thereafter, impurity (phosphorus) is implanted for the entire surface of the polysilicon film 14 by the use of the ion implanting technique.
In this case, the ions are implanted within the concentration range between 5xc3x971012 and 3xc3x971013 [cmxe2x88x922] and within the accelerating voltage range between 50 and 70 [Kev].
The ion implantation serves to determine the resistance value of the load resistor L1 illustrated in FIG. 1. This implanting condition is important for manufacturing the SRAM device because the resistance value of the load resistor L1 is a factor for determining consuming current during a standby mode in the SRAM device.
Thereafter, the polysilicon film 14 is patterned by the photolithography technique. Successively, impurity (phosphorus) is implanted onto the polysilicon film 14 and the TEOS.BPSG film 10 patterned by the photolithography technique and the ion implanting technique.
In this case, the ions are implanted within the concentration range between 1xc3x971015 and 1xc3x971018 [cmxe2x88x922] and within the accelerating voltage range between 50 and 70 [Kev].
Herein, the polysilicon film 14 serves as the load resistor L1 illustrated in FIG. 1 while the ion implantation serves to form the wiring pattern for the power supply voltage Vcc in FIG. 1.
Further, a silicon oxide film 15 is deposited to a thickness within the range between 100 and 150 nm on the TEOS.BPSG film 10 and the polysilicon film 14 by the CVD technique.
Thereafter, the TEOS.BPSG film 16 is deposited to a thickness within the range between 500 and 1500 nm by the CVD technique.
In addition, the TEOS.BPSG film 16 is polished by the Chemical Mechanical Polishing (CMP) technique in order to flatten the surface. The flattening process is conducted so that the wiring layer is not short-circuited.
Finally, referring to FIG. 7, a contact hole 17 is opened for the silicon oxide film 9, the TEOS.BPSG film 10, the silicon oxide film 15, and the TEOS.BPSG film 16 by the use of the etching technique.
Thereafter, the contact hole 17 is buried with W (tungsten) serving as the high-melting point metal by sequentially depositing a titanium film and a titanium nitride serving as the high-melting point metal.
Subsequently, W serving as the high-melting point metal is etched-back by the etch-back technique to deposit Al (aluminum).
At the same time, an Al wiring layer 18 is patterned by the use of the photolithography technique.
Through the above-mentioned steps, the main part of the high-resistance load type memory cell for the SRAM device is completed.
The related technique with respect to such a semiconductor device is, for example, disclosed in Japanese Unexamined Patent Publication (JPA) No. Sho. 62-31155 and Japanese Unexamined Patent Publication (JPA) No. Hei. 8-23037.
In the high-resistance load type memory cell of the SRAM device, when the memory is reduced in size to realize the high-integration, the node capacitance is reduced also.
Thereby, the ratio, in which the voltage V1h is reduced to Vccxe2x88x92Vt by the power supply voltage Vcc, becomes high. Further, the time, in which the voltage V1h restores to the power supply voltage Vcc by the power supply voltage Vcc, also become slow. As a result, the SER resistance is deteriorated.
To avoid the deterioration of the SER resistance, a P-type impurity region having higher concentration than the P-well region may be formed on the entire surface of the memory cell region.
However, this method deteriorates substrate bias characteristic of the transfer transistor. Consequently, it is difficult to actually apply this method for the SRAM device because the high-speed of the SRAM device can not be readily realized.
It is therefore an object of this invention to provide a semiconductor device in which substrate bias characteristic is not deteriorated in a transfer transistor even when a memory is reduced in size.
It is another object of this invention to provide a semiconductor device which is capable of enhancing a SER resistance by increasing node capacitance of a memory cell.
According to this invention, a SRAM device includes at least a transfer transistor, a driving transistor and a load resistor which are commonly connected to a node.
With this structure, a well has a first conductive type, and is placed on a substrate.
Further, a first impurity region has a second conductive type opposite to the first conductive type, and is placed in the well.
Moreover, a second impurity region has the first conductive type and has higher impurity concentration than impurity concentration of the well, and is placed at a lower portion of the first impurity region.
Herein, the node is composed of at least the first impurity region and the second impurity region.
For example, the first conductive type is a P-type while the second conductive type is an N-type.
The SRAM device further comprises a bit line and a word line. The transfer transistor includes a first terminal, a second terminal and a third terminal.
In this condition, the first terminal is connected to the bit line, the second terminal is connected to the node, and the third terminal is connected to the word line.
More specifically, the transfer transistor includes a source, a drain and a gate, the first terminal and the second terminal is any one of the source and the drain, and the third terminal is the gate.
Further, the SRAM device comprises a reference voltage terminal. The driving transistor includes a first terminal and a second terminal, the first terminal is connected to the node, and the second terminal is coupled to the reference voltage terminal.
More specifically, the driving transistor includes a source and a drain, and the first terminal and the second terminal is any one of the source and the drain.
Moreover, the SRAM device comprises a power supply voltage terminal. The load resistor includes a first terminal and a second terminal, the first terminal is connected to the node, and the second terminal is coupled to the power supply voltage terminal.
Further, a node capacitor is coupled to the node. In this event, the node capacitor has a capacitance, and the transfer transistor has a substrate bias characteristic.
Under this circumstance, the second impurity region serves to increase the capacitance without deterioration of the substrate bias characteristic.
In addition, the SRAM device has a soft error resistance, and the second impurity region serves to enhance the soft error resistance.